The 32-bit EFLAGS register contains:
- a group of status flags,
- and a group of system flags.
When binding itself to a new task, the processor loads the EFLAGS register with data from the new task’s TSS.
Interrupt or exception handler
When an interrupt or exception is handled with a task switch, the state of the EFLAGS register is saved in the TSS for the task being suspended.
Following initialization of the processor, the state of the EFLAGS register is 00000002H.
Bits 1, 3, 5, 15, and 22 through 31 of this register are reserved. Software should not use or depend on the states of any of these bits.
- and POPFD.
Some of the flags in the EFLAGS register can be modified directly, using special-purpose instructions. There are no instructions that allow the whole register to be examined or modified directly.
After the contents of the EFLAGS register have been transferred to the procedure stack or EAX register, the flags can be examined and modified using the processor’s bit manipulation instructions (BT, BTS, BTR, and BTC).