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In virtual memory implementation, when a process requests access to its memory, it is the responsibility of the operating system to map the virtual address provided by the process to the physical address where that memory is stored.
The page table is where the operating system stores its mappings of:
- virtual addresses. (Virtual addresses are those unique to the accessing process.)
- to physical addresses. (Physical addresses are those unique to the CPU, i.e., RAM.)
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PTE
Each memory page is described by 1 “page table entries” (PTEs). PTEs are similar to primary key indexes. They describe the location of “this” page. The PTE memory structure is organized in a similar way as an database index. It has three layers, and up to three pointers need to be accessed to find where a given page is located. This can be a very time-consuming operation, so each modern CPU has a fixed number of Cache entries called the “TLB cache” (Translation Lookaside Buffer). Each PTE entry also takes some small amount of memory. If you have many processes, consuming a lot memory, the memory needed for PTEs can be significant.