An instruction cycle (sometimes called fetch-decode-execute cycle) is the basic operation cycle of a computer.
The CPU requires a fixed number of clock ticks (or clock cycles) to execute each instruction. The faster the clock, the more instructions the CPU can execute per second.
The implementation from a logical point of view can be seen in the computer organization architecture.
From one CPU model to another, the complete pipeline (included all operations) may varied.
In most modern CPUs, the instruction cycle is instead executed concurrently in parallel, as an instruction pipeline: the next instruction starts being processed before the previous instruction is finished, which is possible because the cycle is broken up into separate steps.
Each time the processor's clock pulses (ticks), the control unit does these steps:
- Decode or identify the instruction,
- Stores the result.
- increments the instruction pointer
- check for interrupts
- goes back to step one.
TSC (Timestamp counter)
Each core on a moder CPU has a TSC (Timestamp counter) that counts the number of ticks that have transpired. See Tick count